Includes ST state-of-the-art patented technology Core ? 32-bit Arm? Cortex?-M7 core with doubleprecision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 480 MHz, MPU, 1027 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions Memories ? 128 Kbytes of Flash memory ? 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), 864 Kbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain ? Dual mode Quad-SPI memory interface running up to 133 MHz ? Flexible external memory controller with up to 32-bit data bus: – SRAM, PSRAM, NOR Flash memory clocked up to 133 MHz in synchronous mode – SDRAM/LPSDR SDRAM – 8/16-bit NAND Flash memories ? CRC calculation unit Security ? ROP, PC-ROP, active tamper, secure firmware upgrade support, Secure access mode General-purpose input/outputs ? Up to 168 I/O ports with interrupt capability Reset and power management ? 3 separate power domains which can be independently clock-gated or switched off: – D1: high-performance capabilities – D2: communication peripherals and timers – D3: reset/clock control/power management ? 1.62 to 3.6 V application supply and I/Os ? POR, PDR, PVD and BOR ? Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs ? Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry ? Voltage scaling in Run and Stop mode (6 configurable ranges) ? Backup regulator (~0.9 V) ? Voltage reference for analog peripheral/VREF+ ? Low-power modes: Sleep, Stop, Standby and VBAT supporting battery charging Low-power consumption ? VBAT battery operating mode with charging capability ? CPU and domain power state monitoring pins