XCZU4CG-2FBVB900I

XCZU4CG-2FBVB900i

代理商

產(chǎn)品特性

Summary

The Xilinx? Zynq? UltraScale+? MPSoCs

are available in -3, -2, -1 speed

grades, with -3E devices having

the highest performance. The -2LE and -1LI devices can operate at a V

CCINT

voltage at 0.85V or 0.72V and

are screened for lower maximum stat

ic power. When operated at V

CCINT

=  0.85V, using -2LE and -1LI

devices, the speed specification for the L devices is the same as the -2I or -1I speed grades. When

operated at V

CCINT

= 0.72V, the -2LE and -1LI performance and static and dynamic power is reduced.

DC and AC characteristics are specified in extended

(E), industrial (I), and expanded (Q) temperature

ranges. Except the operating temperature range or unl

ess otherwise noted, all the DC and AC electrical

parameters are the same for a particular speed grade

(that is, the timing characteristics of a -1 speed

grade extended device are the same as for a -1 speed grade industrial device). However, only selected

speed grades and/or devices are av

ailable in each temperature range.

All supply voltage and junction temp

erature specifications are representative of worst-case conditions.

The parameters included are common to po

pular designs and typical applications.

This data sheet, part of an overall set of document

ation on the Zynq UltraScale+ MPSoC

Summary

The Xilinx? Zynq? UltraScale+? MPSoCs

are available in -3, -2, -1 speed

grades, with -3E devices having

the highest performance. The -2LE and -1LI devices can operate at a V

CCINT

voltage at 0.85V or 0.72V and

are screened for lower maximum stat

ic power. When operated at V

CCINT

=  0.85V, using -2LE and -1LI

devices, the speed specification for the L devices is the same as the -2I or -1I speed grades. When

operated at V

CCINT

= 0.72V, the -2LE and -1LI performance and static and dynamic power is reduced.

DC and AC characteristics are specified in extended

(E), industrial (I), and expanded (Q) temperature

ranges. Except the operating temperature range or unl

ess otherwise noted, all the DC and AC electrical

parameters are the same for a particular speed grade

(that is, the timing characteristics of a -1 speed

grade extended device are the same as for a -1 speed grade industrial device). However, only selected

speed grades and/or devices are av

ailable in each temperature range.

All supply voltage and junction temp

erature specifications are representative of worst-case conditions.

The parameters included are common to po

pular designs and typical applications.

This data sheet, part of an overall set of document

ation on the Zynq UltraScale+ MPSoC

The Zynq? UltraScale+? MPSoC family is based on the Xilinx? UltraScale? MPSoC architecture. This family of products integrates a feature-rich 64-bit quad-core or dual-core Arm? Cortex?-A53 and dual-core Arm Cortex-R5 based processing system (PS) and Xilinx programmable logic (PL) UltraScale architecture in a single device. Also included are on-chip memory, multiport external memory interfaces, and a rich set of peripheral connectivity interfaces. Processing System (PS) Arm Cortex-A53 Based Application Processing Unit (APU) ? Quad-core or dual-core ? CPU frequency: Up to 1.5GHz ? Extendable cache coherency ? Armv8-A Architecture o 64-bit or 32-bit operating modes o TrustZone security o A64 instruction set in 64-bit mode, A32/T32 instruction set in 32-bit mode ? NEON Advanced SIMD media-processing engine ? Single/double precision Floating Point Unit (FPU) ? CoreSight? and Embedded Trace Macrocell (ETM) ? Accelerator Coherency Port (ACP) ? AXI Coherency Extension (ACE) ? Power island gating for each processor core ? Timer and Interrupts o Arm Generic timers support o Two system level triple-timer counters o One watchdog timer o One global system timer ? Caches o 32KB Level 1, 2-way set-associative instruction cache with parity (independent for each CPU) o 32KB Level 1, 4-way set-associative data cache with ECC (independent for each CPU) o 1MB 16-way set-associative Level 2 cache with ECC (shared between the CPUs) Dual-core Arm Cortex-R5 Based Real-Time Processing Unit (RPU) ? CPU frequency: Up to 600MHz ? Armv7-R Architecture o A32/T32 instruction set ? Single/double precision Floating Point Unit (FPU) ? CoreSight? and Embedded Trace Macrocell (ETM) ? Lock-step or independent operation ? Timer and Interrupts: o One watchdog timer o Two triple-timer counters ? Caches and Tightly Coupled Memories (TCMs) o 32KB Level 1, 4-way set-associative instruction and data cache with ECC (independent for each CPU) o 128KB TCM with ECC (independent for each CPU) that can be combined to become 256KB in lockstep mode On-Chip Memory ? 256KB on-chip RAM (OCM) in PS with ECC ? Up to 36Mb on-chip RAM (UltraRAM) with ECC in PL ? Up to 35Mb on-chip RAM (block RAM) with ECC in PL ? Up to 11Mb on-chip RAM (distributed RAM

產(chǎn)品應(yīng)用

? Consumer Electronics ? Compute and Storage ? Wireless Communications ? Industrial Control Systems ? Automotive System

規(guī)格

	型號	DataSheet	Dimension (mm)	Description

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